1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory devices that prevent conflicts between data read from and data written to the devices.
2. Description of the Related Art
In general, a DDR SDRAM semiconductor device is connected to a DRAM controller. The DRAM controller writes data to and reads data from the DDR SDRAM semiconductor device. The DDR SDRAM semiconductor device includes a memory bank that stores data, a delay locked loop (“DLL”) circuit that generates a clock signal, an output buffer that buffers data stored in the memory bank and outputs the buffered data in synchronization with the clock signal, and an output controller that controls the operation of the output buffer.
FIG. 1 shows a timing diagram, indicated generally by the reference numeral 100, describing a malfunction of a conventional DDR SDRAM semiconductor device when the DRAM controller writes data to the DDR SDRAM semiconductor device. Hereinafter, the reason for the malfunction will be described with reference to FIG. 1.
Once the DRAM controller applies a read command RD to the DDR SDRAM semiconductor device and a CAS latency elapses, the output buffer outputs data DQR. At this time, the data DQR is output from the output buffer in synchronization with a clock signal CLK_DLL output from the DLL circuit.
The output controller receives the clock signal CLK_DLL and the read command RD. While receiving the clock signal CLK_DLL, the output controller activates the output buffer when the read command RD is active and deactivates the output buffer when the read command RD is inactive. This operation prevents unnecessary power consumption by the output buffer.
Once a precharge command PR is applied to the memory bank after the output buffer has output data DQR, the clock signal CLK_DLL is not output to the output controller any more. This state is maintained while the DLL circuit is reset and completes a locking operation on a signal input to the DLL circuit, i.e., during a period tD. At this time, the output controller should deactivate the output buffer because the read command RD is inactive. However, since the clock signal CLK_DLL has not been input to the output controller, the output controller may erroneously apply an active read command RD latched therein to the output buffer to activate the output buffer. Then, if data DQR generated in the DDR SDRAM semiconductor device is input to the output buffer, the output buffer outputs data DQR to the DRAM controller without receiving the read command RD.
Thereafter, when a write command WR becomes active, and thus, the DRAM controller writes data DQW to the DDR SDRAM semiconductor device, a conflict occurs between data DQW written to the DDR SDRAM semiconductor device and data DQR output from the DDR SDRAM semiconductor device. Such a conflict causes malfunction of the DDR SDRAM semiconductor device.